FIG. 4 is a diagram illustrating the configuration of a SRAM (Static Random-Access Memory) cell of a dual-port static memory circuit in which each cell is composed of eight transistors. As shown in FIG. 4, the memory cell includes a PMOS transistor Q2 (a load) and an NMOS transistor Q1 (a driver transistor) connected in series between a first power supply VDD and a second power supply VSS, and a PMOS transistor Q4 (a load) and an NMOS transistor Q3 (a driver transistor) connected in series between the power supplies VDD and VSS. Commonly coupled drains (N1) of the PMOS transistor Q2 and NMOS transistor Q1 are connected to commonly coupled gates of the PMOS transistor Q4 and NMOS transistor Q3, and commonly coupled drains (N2) of the PMOS transistor Q4 and NMOS transistor Q3 are connected to commonly coupled gates of the PMOS transistor Q2 and NMOS transistor Q1. Provided between the node N1 and bit lines DTA and DTB are A-port and B-port access transistors Q5 and Q6 whose gates are connected to word lines WLA and WLB, respectively, and provided between the node N2 and complementary bit lines DBA and DBB are A-port and B-port access transistors Q7 and Q8 whose gates are connected to the word lines WLA and WLB, respectively.
In the dual-port static memory circuit having the SRAM cell illustrated in FIG. 4, each of the ports A and B is used as an I/O port where reading and writing are performed (in which case the two ports are capable of simultaneous READ). The port A may be used as a write-only port and the port B may be used as a read-only port (or vice versa). With regard to a multiport memory circuit, refer also to the description in Patent Document 1.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-A-1-296486
The following analysis is given by the present invention. The disclosures of the above-mentioned Patent Document are herein incorporated by reference thereto, and regarded as part of the disclosure of the present invention.
The problem with the dual-port static memory circuit having the SRAM cell shown in FIG. 4 is that the memory cannot be tested in the worst case with regard to operating margin. This will now be described. It should be noted that the description that follows is based upon the results of analysis conducted by the Inventor.
In FIG. 4, there is illustrated an example of operation of the SRAM cell in a case where the ports A and B are read simultaneously, in which currents Icell_A and Icell_B flow simultaneously from the bit lines DTA and DTB to the driver transistor Q1 within the SRAM cell. In a case where the same row is accessed by the ports A and B simultaneously, the word lines WLA and WLB of both ports A and B go HIGH simultaneously. Hence, port A access transistors Q5 and Q7 and port-B access transistors Q6 and Q8 turn on simultaneously. It should be noted that in the configuration shown in FIG. 4, it is assumed that the bit-line pairs (DTA, DBA) and (DTB, DBB) of both ports were pre-charged to the HIGH level before activation of the select word line.
Since the driver transistor Q1 in the SRAM cell have to pull-down both bit lines DTA and DTB of ports A and B to the LOW level, the pull-down characteristic of bit lines DTA and DTB is deteriorated in comparison with a case where the bit line of one port is pulled down to the LOW level. Consequently, the value of bit-line difference potential [ΔVBL: difference potential between bit-line pair (DTA, DBA) and between bit-line pair (DTB, DBB)] read by a sense amplifier (not shown) is reduced so that operating margin decreases and minimum operating voltage worsens.
The longer becomes a period of time in which the ON states of the port A and port-B access transistors Q5 and Q6 overlap, the greater becomes the extent of the decline in the value of the bit-line difference potential ΔVBL. Accordingly, the time at which the potentials at the word lines of both ports rise simultaneously is the point at which the cell-data read margin is most severe and the minimum operating voltage is at its worst value.
FIG. 5A is a graph illustrating the relationship between a difference Δt [=t(WLA−WLB)] between rise timings of the word lines WLA and WLB of the ports A and B and the bit-line difference potential ΔVBL (V|DTA−DBA|, V|DTB−DBB|). It will be appreciated that in a case where the rise timings of the word lines WLA and WLB of the ports A and B overlap (see FIG. 5C), ΔVBL is minimum (see the valley of ΔVBL in FIG. 5A).
Specifically, when one bit line of the bit-line pairs is HIGH based upon the cell data, the driver transistor of the SRAM cell discharges the other bit line of the bit-line pairs to the LOW level. However, in a case where the other bit lines (e.g., DTA, DTB) of the bit line pairs of ports A and B are pulled down to LOW simultaneously by one driver transistor, the potential difference between the bit-line pairs diminishes and the speed of enlarging the potential difference becomes slow, as illustrated in FIG. 5C, in comparison with a case where just the bit line of one port is pulled down to the LOW level, from the standpoint of the current driving capability of the driver transistor. By contrast, if the timings at which the word lines WLA and WLB of ports A and B are activated (namely the rise timings) are shifted forward or backward in terms of time, the bit-line difference potential ΔVBL is large (see FIG. 5B).
A test of a memory device conducted prior to shipment thereof, should employ worst case testing in which the bit-line difference potential ΔVBL is minimum.
However, for the following two reasons, a case occurs where the word lines of both ports cannot be driven at the same timing and the operating margin does not exhibit its worst value:
(a) owing to variations between elements in a chip, skew (a shift in timing) occurs between ports in the path from a BIST (Build-In Self-Test) apparatus to the memory; and
(b) skew of an internal clock for activating a word line, ascribable to the physical layout in the memory, occurs. This will be described below in further detail with reference to the drawings.
FIG. 6 illustrates a typical example of the configuration of a word-line control unit in a static memory circuit having the SRAM cell shown in FIG. 4. Shown in FIG. 6 is an example of the configuration of a clock-synchronized dual-port static memory circuit in which word-line activation timing is controlled based upon an input clock signal.
With reference to FIG. 6, clock signals CLKA and CLKB supplied to clock terminals (A) and (B), respectively, are received by buffers 101 and 102, respectively, and internal clock signals ICLA and ICLB are output from the buffers 101 and 102, respectively.
XKA and XEA of address select signals (A) (row address) that select word line WLA of port A are outputs of a main pre-decoder (not shown) and a sub pre-decoder (not shown) of an X-address decoder (row-address decoder) for port A, respectively.
XKB and XEB of address select signals (B) (row address) that select word line WLB of port B are outputs of a main pre-decoder (not shown) and a sub pre-decoder (not shown) of an X-address decoder (row-address decoder) for port B, respectively.
There are provided a NAND gate 103 that receives XKA and XEA of the address select signal (A), and a CMOS transfer gate 105 comprising a PMOS transistor having a gate at which the output of the NAND gate 103 is received, and an NMOS transistor having a gate that receives a signal that is the result of inverting the output of the NAND gate 103 by an inverter 104. When XKA and XEA are both HIGH, the output of the NAND gate 103 is LOW. As a result, the CMOS transfer gate 105 turns on and transfers the internal clock signal ICLA, and the word line WLA is raised to the high potential by an inverter 107 and an inverting buffer (inverting-type word driver) 108. In a case where XKA and XEA are both other than HIGH (i.e., in a case where either one is LOW), the output of the NAND gate 103 goes HIGH, an NMOS transistor 106 turns on, the input to the inverter 107 is fixed at the LOW level and the word line WLA is set to the LOW level. The period of time during which the select word line is activated corresponds to the duration of the HIGH pulse of the internal clock signal ICLA. The configuration is similar with regard to the address select signal (B) of port B.
FIG. 7 is a diagram schematically illustrating a test of a static memory circuit by BIST. In FIG. 7, IOA and IOB each include a write amplifier (not shown) and a sense amplifier (not shown) for respectively writing and reading data of port A and port B of a SRAM cell array (SRAM CELL). Control units CNTA and CNTB receive clock signals CLKA and CLKB and perform timing control of selected word lines of port A and port B, respectively. WLDA and WLDB include X-address decoders for decoding row addresses of port A and port B, respectively and word drivers for driving select word lines of port A and port B, respectively. When the test is conducted, clock signals from a BIST circuit 202 are distributed via clock distribution paths (clock buffer groups 203 and 204) and arrive at respective clock terminals CLKA and CLKB of port A and port B of a memory circuit 201.
In this case, a clock skew is generated between the ports A and B owing to parameter variations betweens the BIST circuit 202 and memory circuit 201.
Further, a skew between the internal clocks of the two ports is generated owing to the physical layout within the memory circuit 201. For example, since the path of the clock from the clock terminal CLKA to the word line WLA has a path length different from the path of the clock from the clock terminal CLKB to the word line WLB, a skew is generated between the internal clocks ICLA and ICLB.
For these reasons, it is difficult to realize a test in which the word line WLA of the port A and the word line WLB of the port B are made to rise simultaneously.
Further, even in a case where a memory device is tested using not a BIST circuit but test by a tester that has a skew between pins calibrated, similar problems arise owing to a skew between the internal clocks of the two ports ascribable to the physical layout within the memory circuit and a skew between clock terminals of the ports A and B of the memory circuit 201 within the semiconductor device.
In a memory device provided with a cell including a plurality of ports in accordance with the related art, it is difficult to exercise control so as to cause word lines of a plurality of ports to rise simultaneously when the device is tested, as set forth above. This means that the device cannot be tested in the worst state. As a result, pass/fail decision accuracy (measurement precision) is limited, and this leads to a limitation on an improvement in product yield and reliability.